pattern_generator
Overview
can produce pattern data for jesd (ADC), and for the LMC channelizer, beamformer, intergrated channelizer, intergrated beamformer data
Python Class & Methods Index
- class pyfabil.plugins.tpm.pattern_generator.TpmPatternGenerator(board, **kwargs)[source]
Pattern generator
- channelize_pattern(pattern)[source]
Change the frequency channel order to match che channelizer output :param pattern: pattern buffer, frequency channel in increasing order
- clear_signal_adder(stage)[source]
Clear signal adder. Set to zero the signal adder of each signal. :param stage: stage where write clear to signal adders
- get_pattern(stage='channel')[source]
Read pattern from FPGA internal BRAM buffer :param stage: stage where write the pattern: jesd, channel or beamf
- initialise(nof_inputs_per_fpga=16)[source]
Initialise Pattern Generator with default incremental pattern
- set_pattern(buff, stage='channel')[source]
Write pattern in FPGA internal BRAM buffer :param buff: pattern buffer, each element represents an output value :param stage: stage where write the pattern: jesd, channel or beamf
- set_random_pattern(stage='channel', seed=0)[source]
Write a randmon pattern in FPGA internal BRAM buffer :param stage: stage where write the pattern: jesd, channel or beamf :param seed: seed for random number generator generator
- set_signal_adder(adder_list, stage)[source]
Set signal adder. For each signal its pattern is constructed by adding a value to the pattern of input 0. :param adder_list: list of 64 adder (one adder per each signal and muxed value = 16*4) :param stage: stage where write the pattern: jesd, channel or beamf
- start_pattern(stage)[source]
Start pattern. :param stage: stage where start the pattern: jesd, channel or beamf